Segmented channel routability via satisfiability

On segmented channel routability

We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field programmable gate array (FPGAs). Our approach transforms the routing task into a single large Boolean equation such that any assignment of input variables that satisfies the equation specifies a valid routing. It considers ...

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits...

Solving Satisfiability Via Boltzmann Machines

Modal Satisfiability via SMT Solving

Modal logics extend classical propositional logic, and they are robustly decidable. Whereas most existing decision procedures for modal logics are based on tableau constructions, we propose a framework for obtaining decision procedures by adding instantiation rules to standard SAT and SMT solvers. Soundness, completeness, and termination of the procedures can be proved in a uniform and elementa...

The complexity of segmented channel routing

The segmented channel routing problem arises in the wiring and the physical design automation for Field Programmable Gate Arrays (FPGA’s), a new type of electrically programmable VLSI. It may also be applicable to configurahle multiprocessors. This new routing problem poses interesting algorithmic problems. In a previous paper of IEEE TRANSACTION ON COMPUTER-AIDED DESIGN, the study of the compl...